1. Field of the Invention
The present invention generally relates to an image display apparatus capable of gradation-displaying information data on a dot-matrix type display panel such as a liquid crystal display (LCD). More specifically, the present invention is directed to an improvement in a signal electrode drive circuit employed in such a liquid crystal display.
2. Description of the Related Art
In a conventional image display apparatus capable of gradation-displaying information data on a dot-matrix type display panel such as a liquid crystal display, a 2.sup.n -gradation display is performed by supplying n-bit data to a signal electrode drive circuit ("n" being an integer). To increase the number of the pixels (picture elements) of the display panel, the data transfer frequency must be accordingly increased. In this case, the operation frequency of the signal electrode drive circuit must be set to be high in accordance with the signal transfer frequency. However, if the operation frequency of such an image display apparatus is increased, then a higher graded circuit is required. As a result, various limitations may be provided with the circuitry, and higher power is consumed and furthermore occurrence of noise is emphasized.
FIG. 1 illustrates a major circuit arrangement of a conventional liquid crystal drive circuit (segment driver circuit). Such a signal electrode drive circuit is known from, for instance, U.S. Pat. No. 4,581,654.
The circuit arrangement shown in FIG. 1 is constructed as follows. There is employed a shift register 11. Shift register sections 11a, 11b, --of each stage are constructed in a three-bit arrangement, for example, by D-type flip-flops. In this shift register 11, the 3-bit data D1 to D3 which are transferred from an A/D (analog-to-digital) converter (not shown) employed in front of these shift registers, are read out by 2-phase clock pulses .phi.1 and .phi.2, and then sequentially shifted along the shift register sections 11a, 11b, --. When 1-line data has been set in these register sections 11a, 11b, --of the shift register 11, a latch pulse .phi..sub.L is applied thereto, and thus the data held in these shift register sections 11a, 11b, --are latched in the latch circuits 12a, 12b, --. Thereafter, the data are transferred to a drive circuit (not shown). In the drive circuit, for instance, an 8-gradation drive signal is produced based upon the data latched in these latch circuits 12a, 12b, --, whereby the segment electrodes of the liquid crystal display panel are driven for displaying the desired data.
However, in the conventional drive circuit with the above-described circuit arrangement, the clock pulses .phi.1 and .phi.2, and the data transfer frequency for shifting the data in the shift register sections 11a, 11b, --, of the shift register 11 are equal to the sampling frequencies of the input data D1 to D3 As a consequence, the transfer frequency is limited to the operation frequency of the signal electrode drive circuit, so that this transfer frequency cannot be selected to be so high. To the contrary, if the signal electrode drive circuit is designed to be operative under a higher frequency, high-graded circuitry is necessarily required, resulting in an expensive circuit cost. In accordance with the higher operation frequency, larger power consumption occurs and much noise is produced.